ARM EN0-001 Exam Questions Free Practice Test

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Questions # 41:

A software profiling tool records the address held in the Program Counter (PC) every 1 ms. The software function that resides at each recorded address can be determined by the profiling tool. The percentage of time spent in each function is calculated from the percentage of recorded addresses where each function is resident.

Which one of the following statements is FALSE?

Options:

The tool shows an estimate of the percentage of time spent in each function

The tool identifies all functions executed by the application

The function with the highest percentage is a good candidate for optimization

The results will be more accurate on a processor running at 250 MHz. than one running at 2 GHz

Expert Solution

Questions # 42:

Which of the following statements regarding Strongly-ordered memory is architecturally FALSE?

Options:

Address locations marked as Strongly-ordered memory are never held in a cache

The architecture does not permit speculative data accesses to Strongly-ordered memory

A write to Strongly-ordered memory is permitted to complete before it reaches the peripheral or memory component accessed by the write

The number and size of accesses to Strongly-ordered memory must be the same as that specified by the program

Expert Solution

Questions # 43:

Which of the following is a REQUIRED feature in the ARMv7 architecture?

Options:

The Thumb-2 instruction set

NEON

Integer division instructions

A memory management unit

Expert Solution

Questions # 44:

Which one of the following debug methods is the least intrusive for analyzing a timing related bug?

Options:

Place breakpoints on strategic locations to locate the problem area

Instrument the code with print statements to locate the problem area

Use debug hardware to place watchpoints on strategic data memory locations

Use trace hardware to capture a trace log up to the point of the crash

Expert Solution

Questions # 45:

In an ARMv7-A processor, which control register is used to enable the Memory Management Unit (MMU)?

Options:

The ACTLR

The SCTLR

The TTBCR

The CONTEXTIDR

Expert Solution

Questions # 46:

The instruction LDR pc, [ r1 ] takes longer to execute on a particular system, than the instruction LDR r0, [ r1 ]. In both cases, r1 points to the same address in external memory.

Which of the following is the most likely explanation of why it takes more cycles?

Options:

The value read from address r1 must be passed from the data side of the processor to the instruction side

The LDR pc, [r1] causes the instruction pipeline to be flushed, but the LDR r0, [r1] does not

The LDR pc, [ r1 ] instruction requires additional alignment checking, as the result must be half word-aligned (Thumb) or word-aligned (ARM)

The LDR r0, [r1] can be speculatively executed, but the LDR pc, [r1] instruction cannot be speculatively executed

Expert Solution

Questions # 47:

According to the EABI. what would the C size of () operator return when given the following structure?

Question # 47

Options:

Expert Solution

Questions # 48:

The disassembly of a program written in C shows calls to the function__aeabi_fadd. Which one of these compiler floating point options could have been used?

Options:

Hard floating-point linkage

Soft floating-point linkage without floating-point hardware

Hard floating-point linkage with optimization for space

Soft floating-point linkage with floating-point hardware

Expert Solution

Questions # 49:

The effect of clicking the Stop button in a debugger is to:

Options:

Put the processor(s) into debug state.

Force the processor to execute a BKPT instruction

Hold the processor in a Reset condition

Re-initialize the memory contents.

Expert Solution

Questions # 50:

An interrupt handler contains the following instruction sequence at the end. The purpose of these instructions is to clear the interrupt request in the interrupt controller and then safely re-enable interrupts.

STR r0, [r1] ; write to interrupt controller register to clear interrupt request

CPSIE i ; re-enable IRQ interrupts

Which of the following instructions should be placed at position in order to ensure that the interrupt controller sees the write before interrupts are re-enabled?

Options:

DMB

DSB

ISB

NOP

Expert Solution

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