What architecture does the ARM11 MPCore implement?
In a multi-processor system, there are four processors numbered 0, 1, 2 and 3. The state of the processors is as follows:
CPU 0 and 1 are sleeping in low-power state following a WFI instruction. . CPU 2 is executing program code.
CPU 3 is sleeping in low-power state following a WFE instruction.
CPU 2 executes a SEV instruction. What is the effect on the system?
In which type of storage will the compiler preferentially place frequently accessed variables?
According to the AAPCS, which of the following statements is TRUE with regard to preservation of register values by a function?
When the processor is executing in Thumb state, which of the following statements is correct about the values stored in R15?
The Cortex-A9 processor has 6 breakpoint units and 4 watchpoint units. What is the maximum number of breakpoints the debugger can set on code in ROM?
Cortex-A series processors contain event counting hardware which can be used to profile and benchmark code. The counters for these are programmed using:
In a Cortex-A9 processor, when the Memory Management Unit (MMU) is disabled, which of the following statements is TRUE? (VA is the virtual address and PA is the physical address)
When a linker is removing unused sections during a static link (for example, -remove or -gc-sections), it finds the sections to keep by following all relocations starting from:
According to the AAPCS, how many bytes are used to store a C variable of type 'int' in memory?
