What type of debug point would you set when debugging flash memory or ROM?
Consider the following code sequence, executing on a processor which implements ARM Architecture v7-A.
LDR r0, [r1]
STR r0, [r2]
STR r3, [r3]
R1 points to a location in normal memory. R2 and R3 point to device memory.
Which of the following statements best describes the ordering rules which apply to this sequence?
When debugging an embedded Linux system, which one of the following techniques can be used to halt a single user thread, while allowing other threads to continue to run during the debug process?
Which one of the following statements is TRUE for monitor mode debugging?
In the ARM instruction set what is the maximum branch distance for a Branch or Branch and Link instruction?
A deeply embedded real-time industrial control system is missing some hard real-time interrupt deadlines. Which of the following performance analysis techniques is the most suitable for identifying which routines are causing the problem?
When timing a critical function for an algorithm, using platform time functions such as get time of day (), the result is unpredictable; there is significant variance in the measured time between different runs of the benchmark. Which of the following strategies would improve the accuracy of the measurement?
Which of the following best describes the relationship between Tightly Coupled Memories (TCM), Level 1 (L1) and Level 2 (L2) cache memory systems?
A Programmer's View CPU model usually provides:
Which of the following techniques can be used to obtain a precise count of clock cycles when profiling software over an arbitrarily long period of time using the Performance Monitoring Unit?
