Consider a sequence of five independent instructions running on a pipelined processor. There are no interlocks and no data dependencies between instructions, and each instruction takes one cycle to execute. The processor has three pipeline stages and is not superscalar.
How many cycles does it take to fetch, decode and execute all five instructions in sequence, assuming that there are no pipeline stalls?
The Memory Protection Unit (MPU) of Cortex-R4 performs which of the following tasks?
In an ARMv7 processor that includes the Advanced SIMD (NEON) extension, how many single precision floating point values can be stored in the Q0 register?
Which of these items is typically shared between threads running in the same Operating System (OS) process?
In a single-processor system, which of these operations requires a barrier instruction to guarantee correct operation?
When should an ISB instruction be used?
How many ARM core registers and PSRs (Program Status Registers) are available to the programmer in User mode on a Cortex-A9?
Which of the following register values would cause an unaligned access when the instruction LDRH r0, [r1] is executed?
Which of the following memory attributes, specified in a translation table entry, could be used to protect a page containing a read-sensitive peripheral from speculative instruction fetches?
In an operating system environment, most applications are executed in which processor mode?
