The value read from address r1 must be passed from the data side of the processor to the instruction side

The LDR pc, [r1] causes the instruction pipeline to be flushed, but the LDR r0, [r1] does not

The LDR pc, [ r1 ] instruction requires additional alignment checking, as the result must be half word-aligned (Thumb) or word-aligned (ARM)

The LDR r0, [r1] can be speculatively executed, but the LDR pc, [r1] instruction cannot be speculatively executed