1. Home
  2. ARM
  3. AAE
  4. EN0-001
  5. ARM Accredited Engineer Questions and Answers

Pass the ARM AAE EN0-001 Questions and answers with CertsForce

 ARM Exams      Go to Exam Detail      Get Premium Access
Viewing page 1 out of 7 pages
Viewing questions 1-10 out of questions
Questions # 1:

A Just-In-Time compiler writes instructions to a region of memory that is configured using a writeback cache strategy. For the locations that have been written, what is the MINIMUM cache maintenance that MUST be performed before the new instructions can be reliably executed?

Options:
A.

Instruction cache clean only

B.

Instruction cache invalidate only

C.

Data cache clean and instruction cache invalidate

D.

Data cache invalidate and instruction cache invalidate

Questions # 2:

In Architecture ARMv7-A which one of the following has a known physical address at power-on reset?

Options:
A.

The exception vector table

B.

The Memory Management Unit (MMU) translation table

C.

The Stack Pointer (SP)

D.

The System Control Register (SCTLR)

Questions # 3:

The following ARM instruction can be used to return from an exception:

movs pc, lr

Apart from the program counter, which register is updated by this instruction?

Options:
A.

Ir

B.

r0

C.

CPSR

D.

SCTLR

Questions # 4:

Implementing loops using a decrementing counter which exits the loop when a counter reaches zero can be beneficial for power and performance. This is because:

Options:
A.

A simpler branch instruction can be used.

B.

Decrementing variables uses less power than incrementing them.

C.

The decrement and branch operations can be encoded as a single instruction.

D.

The loop termination condition check can be integrated into the subtract operation.

Questions # 5:

In the Generic Interrupt Controller (GIC), when an interrupt is requested, but is not yet being handled, it is in which of the following states?

Options:
A.

Inactive

B.

Active

C.

Pending

D.

Edge-triggered

Questions # 6:

The Performance Monitoring Unit (PMU) of a Cortex-A9 processor permits direct measurement of which one of the following?

Options:
A.

Cache Size

B.

Clock Speed

C.

Program size

D.

Numbers of instructions executed

Questions # 7:

In an ARMv7-A processor, with which level of the memory system is the Memory Management Unit (MMU) associated?

Options:
A.

Level 1

B.

Level 2

C.

Level 3

D.

Level 4

Questions # 8:

Which TWO of the following interrupt types does a Generic Interrupt Controller (GIC) support? (Choose two)

Options:
A.

Interrupt from a private peripheral to a processor

B.

Interrupt from a processor to a private peripheral

C.

Interrupt from a shared peripheral to a processor

D.

Interrupt from a processor to a shared peripheral

E.

Interrupt from a private peripheral to a shared peripheral

F.

Interrupt from a shared peripheral to a private peripheral

Questions # 9:

When developing a product using the standard ARM C library, what is the minimum effort required to re-target all platform-specific functions in the library?

Options:
A.

Replace all functions which use semi-hosting

B.

Locate the stack in an area of RAM

C.

Set the locale variable appropriately

D.

All functions in the standard library must be rewritten

Questions # 10:

Which of the following statements best describes a Board Support Package (BSP)?

Options:
A.

PC interface hardware for configuring a boot monitor

B.

Hardware specific source code needed for operating system support

C.

A working port of Linux for a specific hardware platform

D.

Debugging hardware and software supplied with a development board

Viewing page 1 out of 7 pages
Viewing questions 1-10 out of questions